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fn6799 rev 4.00 page 1 of 25 february 18, 2016 fn6799 rev 4.00 february 18, 2016 ISL9440B, isl9440c triple step-down pwm and single linear controller with programm able soft-start datasheet the ISL9440B and isl9440c are quad-output synchronous buck controllers that integrate three pwm controllers and one low drop-out linear regulator controller, which are full featur ed and designed to provide multi-rail power for use in products such as cable and satellite se t-top boxes, voip gateways, cable modems, and other home connectivity products as well as a variety of industrial and general purpose applications. each output is adjustable down to 0.8v. the pwms are synchronized at 180 out-of- phase thus, reducing the rms input current and ripple voltage. the ISL9440B and isl9440c offer programmable soft-start, independent enable inputs for ease of supply rail sequencing, and integrated uv /ov/oc/ot protections in a space conscious 5mmx5mm q fn package. an early warning function is offered to output a logic signal to warn the system to back up data when input voltage falls below a certain level. the ISL9440B and isl9440c utilize internal loop compensation to keep minimu m peripheral components for compact design and a low total solution cost. these devices are implemented with current mod e control with feed-forward to cover various applications even with fixed internal compensations. table 1 shows the difference in terms of isl944xx family features. features ? three integrated synchro nous buck pwm controllers - internal bootstrap diodes - internal compensation ? independent control for each regulator and programmable output v oltages; independent enable/shutdown/soft-start ? fixed switching frequen cy: 300khz(b), 600khz(c) ? adaptive shoot-through pro tection on all synchronous buck controllers ? pre-biased output start-up capability ? out-of-phase switching to reduce input capacitance (0/180/0) ? no external current sense resistor - uses lower mosfets r ds(on) ? current mode controller with voltage feed-forward ? complete protection - overcurrent, overvoltage, undervoltage lockout, over-temperature ? cycle-by-cycle current limiting ? wide input voltage range - input rail powers vin pin: 5.6v to 24v - input rail powers vcc_5v pin (vin tied to vcc_5v, for 5v input applications): 4.5v to 5.6v ? early warning on input voltage failure ? integrated reset function ? pb-free (rohs compliant) applications ? satellite and cable set-top boxes ? cable modems ? vox gateway devices ? nas/san devices ? atx power supply related literature ? technical brief tb389 pcb land pattern design and surface mount guidelines for qfn (mlfp) packages table 1. part number early warning switching frequency (khz) soft-starting time (ms) isl9440 yes 300 1.7 isl9440a yes 600 1.7 isl9441 no 300 1.7 ISL9440B yes 300 programmable isl9440c (no longer available or supported) yes 600 programmable
ISL9440B, isl9440c fn6799 rev 4.00 page 2 of 25 february 18, 2016 pinout ISL9440B, isl9440c (32 ld 5x5 qfn) top view ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (rohs compliant) pkg. dwg. # ISL9440Birz 9440b irz -40 to +85 32 ld 5x5 qfn l32.5x5b isl9440cirz (no longer available, recommended replacement: isl9440irz) 9440c irz -40 to +85 32 ld 5x5 qfn l32.5x5b notes: 1. add -t for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ speci al pb-free material sets, molding compounds/die attach material s, and 100% matte tin plate plus anneal (e3 terminat ion finish, which is rohs com pliant and compatible with both snpb and pb-free soldering oper ations). intersil pb-free products are msl classified at pb-free peak reflow temp eratures that meet or exceed the pb-free requirements of ipc/je dec j std- 020. 3. for moisture sensitivity level (msl), please see device infor mation page for ISL9440B , isl9440c . for more information on msl please see techbrief tb363. phase1 boot1 ugate1 lgate1 lgate2 ugate2 boot2 phase2 g4 ldofb sgnd ocset2 fb2 en/ss2 ocset3 fb3 isen1 pgood vcc_5v vin en/ss1 fb1 ocset1 rst isen2 pgnd lgate3 ugate3 boot3 phase3 isen3 en/ss3 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 910111213141516
fn6799 rev 4.00 page 3 of 25 february 18, 2016 ISL9440B, isl9440c block diagram pwm1 oc1 vcc_5v vcc_5v vcc_5v ocp oc2 channel 2 fb2 pwm2 oc3 oc2 oc1 vcc_5v pgnd error amp 1 fb1 180k + 0.8v 18.5pf 1400k ref 16k _ + isen2 ocset2 2 clock cycles same state for required to latch overcurrent fault channel 3 pwm3 oc3 fb3 isen3 ocset3 fb3 fb2 fb1 fb4 vin ov uv pgood phase1 ugate1 boot1 lgate1 adaptive dead-time v/i sample timing vin pgnd rst vin vcc_5v sgnd adaptive dead-time phase2 ugate2 boot2 lgate2 pgnd v/i sample timing vcc_5v vcc_5v vcc_5v isen1 sample current sample current + 1.75v reference ocset1 duty cycle ramp generator pwm channel phase control pgood - + - + - + - + g4 + 0.8v reference ldofb v e g m *v e adaptive dead-time phase3 ugate3 boot3 lgate3 pgnd v/i sample timing channel 1 por fault latch reference enable soft-start bias supplies early warning en/ss1 1.55a en/ss1 en/ss1 en/ss2 en/ss3 1.3v ref en/ss3 en/ss2 uv (see note 10)
ISL9440B, isl9440c fn6799 rev 4.00 page 4 of 25 february 18, 2016 typical application - ISL9440B + pgood +19v ugate2 phase2 ISL9440B + cin1 r5 c6 30 25 29 6 lgate2 15 isen2 r4 c3 boot2 vin 24 32 r6 31 fb1 ugate1 phase1 + c5 lgate1 isen1 r3 c2 boot1 r2 ocset3 vcc_5v 3 1 28 27 26 4 l2 13 sgnd q2 vout1 r1 q4 fb2 vout2 q4 r9 r10 c12 vout4 r15 +2.5v, 800ma +3.3v, 15a +3.3v cin3 cin5 l1 c1 + 5.0v, 15a r12 c11 vcc_5v v r17 vout2 150f 150k 1.5h 2.2h rjk0301dpb rjk0301dpb 100k 10k 31.6k 2.0k 2.0k 20k 105k 0.22f 10f 4.7f 21.5k 10k 100f si4423dy 330f 10f 0.22f 0.22f 51 330f ugate3 phase3 + r7 c9 19 lgate3 isen3 r11 c8 boot3 18 r8 22 21 20 l3 16 q6 fb3 vout3 +12v, 12a 3.3h 10k 140k 1.5k 180f 0.22f cin7 10f +19v 7 ocset1 r13 150k 12 ocset2 r14 150k 9 10 g4 ldofb 11 5 14 17 pgnd 23 2 pgood 8 rst vcc_5v v r16 100k + c4 330f + c7 330f cinf 0.47f + 330pf cff3 rst en/ss1 en/ss2 en/ss3 c ss3 c ss2 22nf 22nf c ss1 22nf cin2 150f + cin4 10f cff1 220pf cff2 220pf rjk0305dpb q1 q3 rjk0305dpb q5 rjk0301dpb rjk0304dpb cin6 10f rinf1 + c10 180f
ISL9440B, isl9440c fn6799 rev 4.00 page 5 of 25 february 18, 2016 typical application - isl9440c + pgood +12v ugate2 phase2 isl9440c + cin1 r5 co2 30 25 29 6 lgate2 15 isen2 r4 c3 boot2 vin 24 32 r6 31 fb1 ugate1 phase1 + co1 lgate1 isen1 r3 c2 boot1 r2 ocset3 vcc_5v 3 1 28 27 26 4 l2 13 sgnd q1 vout1 r1 q2 fb2 vout2 q4 r8 r9 c6 vout4 r17 +2.5v, 800ma +3.3v, 6a +3.3v cin2 cin3 l1 c1 +1.0v, 6a r7 c4 vcc_5v v r14 vout2 100f 200k 1.8h 1.0h irf7907 irf7907 100k 10.7k 34k 3.09k 1.82k 102k 25.5k 0.1f 10f 4.7f 21.5k 10k 100f fds8433a 330f 10f 0.1f 0.1f 51 330f ugate3 phase3 + r11 co3 19 lgate3 isen3 r10 c5 boot3 18 r12 22 21 20 l3 16 q3 fb3 vout3 +5v, 4a 2.8h irf7907 20k 105k 3.09k 220f 0.1f cin4 10f +12v 7 ocset1 r15 100k 12 ocset2 r16 100k 9 10 g4 ldofb 11 5 14 17 pgnd 23 2 pgood 8 rst vcc_5v v r13 100k cinf 1f + 220pf cff3 rst en/ss1 en/ss2 en/ss3 c ss3 c ss2 22nf 22nf c ss1 22nf cff1 2200pf cff2 47pf 6tpf330m9l 6tpf220mi 6tpf220mi cp1 4700pf
ISL9440B, isl9440c fn6799 rev 4.00 page 6 of 25 february 18, 2016 absolute maximum ratings thermal information vcc_5v to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v vcc_5v output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ma vin to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +28v boot/ugate to phase . . . . . . . . . . . . . -0.3v to vcc_5v + 0.3v phase1,2,3 and isen1, 2, 3, to gnd . . . . . . . . . . . . . . . . . . . . .-5v (<100ns, 10j)/-0. 3v (dc) to +28v en/ss1,en/ss2, en/ss3, fb1, fb2, fb3, to gnd. . . . . . . . . . . . . . . . . . . . . . -0.3v to vcc_5v + 0.3v ldofb, ocset1, ocset2, ocset3, lgate1, lgate2, lgate3, to gnd. . . -0.3v to vcc_5v + 0.3v pgood, rst, g4 to gnd . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v thermal resistance (typical notes 4, 5) ? ja ( c/w) ? jc ( c/w) 32 ld qfn package. . . . . . . . . . . . . . . 31 2.3 maximum junction temperature . . . . . . . . . . . . . . .-55c to +150c maximum operating temperature . . . . . . . . . . . . . . .-40c to +85c maximum storage temperature. . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured in free air with the component mounted on a high e ffective thermal conductivity tes t board with direct attach f eatures. see tech brief tb379. 5. for ? jc , the case temp location is the center of the exposed metal p ad on the package underside. electrical specifications recommended operating conditions unless otherwise noted. refer to block diagram on page 3, typical application - ISL9440B on page 4 and typical application - isl 9440c on page 5. v in = 5.6v to 24v, or vcc_5v = 5v 10%, c_vcc_5v = 4.7f, t a = -40c to +85c, typical values are at t a = +25c. parameter test conditions min (note 11) typ max (note 11) units v in supply input voltage range 5.6 12.0 24.0 v input voltage range v in = vcc_5v (note 10) 4.5 5.0 5.6 v vcc_5v supply (note 6) operation voltage 4.5 5.0 5.6 v internal ldo output voltage v in > 5.6v, i l = 60ma 4.5 5.0 5.5 v maximum supply current of internal ldo v in = 12v 60 ma v in supply current shutdown current (note 7) en/ss1 = en/ss2 = en/ss3 = 0, v in =12v. pgood and rst are floating. 75 110 a operating current (note 8) 3 5 ma reference section internal reference voltage across specified temperature range 0 .8 v reference voltage accuracy across specified temperature range -1 +1 % pwm controller error amplifiers dc gain (note 9) 88 db gain-bw product (note 9) 15 mhz slew rate (note 9) 2.0 v/s pwm regulator switching frequency (ISL9440B) 260 300 340 khz maximum duty cycle (ISL9440B) 93 % minimum duty cycle (ISL9440B) 3% switching frequency (isl9440c) 522 600 678 khz
ISL9440B, isl9440c fn6799 rev 4.00 page 7 of 25 february 18, 2016 maximum duty cycle (isl9440c) 86 % minimum duty cycle (isl9440c) 6% fb bias current (note 9) 50 na peak-to-peak sawtooth amplitude (note 9) v in = 12v 1.6 v v in = 5.5v 0.667 v ramp offset 1 v pwm gate driver channel 1, 2 (ugate1, 2; lgate 1, 2) (note 9) source current 800 ma sink current 2000 ma upper drive pull-up vcc_5v = 5.0v 4 8 ? upper drive pull-down vcc_5v = 5.0v 1.6 3 ? lower drive pull-up vcc_5v = 5.0v 4 8 ? lower drive pull-down vcc_5v = 5.0v 0.9 2 ? rise time c out = 1000pf 18 ns fall time c out = 1000pf 18 ns pwm gate driver channel 3 (ugate3; lgate 3) (note 9) sink/source current 400 ma upper drive pull-up vcc_5v = 5.0v 8.0 12 ? upper drive pull-down vcc_5v = 5.0v 3.2 6.0 ? lower drive pull-up vcc_5v = 5.0v 8 12 ? lower drive pull-down vcc_5v = 5.0v 1.8 3.5 ? rise time c out = 1000pf 18 ns fall time c out = 1000pf 18 ns low drop out controller drive sink current ldofb = 0.76v 50 ma fb threshold voltage ig4 = 21ma 0.800 v amplifier trans-conductance 2a/v ldofb input leakage current (note 9) ldofb = 0.8v 50 na enable1, enable2, enable3 threshold and soft-start current en/ssx enable threshold 1.1 1.3 1.55 v en/ssx soft-start charge current ven/ssx = 1.3v 1.1 1.55 2.0 a power-good monitors pgood upper threshold, pwm 1, 2 and 3 105.5 111 115.5 % pgood lower threshold, pwm 1, 2 and 3 87 91 96 % pgood for linear controller 70 75 80 % pgood low level voltage i_sink = 4ma 0.4 v pgood leakage current pgood = 5v 0.025 1 a electrical specifications recommended operating conditions unless otherwise noted. refer to block diagram on page 3, typical application - ISL9440B on page 4 and typical application - isl 9440c on page 5. v in = 5.6v to 24v, or vcc_5v = 5v 10%, c_vcc_5v = 4.7f, t a = -40c to +85c, typical values are at t a = +25c. (continued) parameter test conditions min (note 11) typ max (note 11) units
ISL9440B, isl9440c fn6799 rev 4.00 page 8 of 25 february 18, 2016 pgood rise time r pullup = 10k to 3.3v 0.05 s pgood fall time r pullup = 10k to 3.3v 0.05 s early warning functions undervoltage lockout rising (vcc_5v pin) 3.40 3.85 4.30 v undervoltage lockout falling (vcc_5v pin) 3.25 3.70 4.15 v early warning voltage rising 5.75 5.95 v early warning voltage falling 5.30 5.55 v rst rst voltage low i_sink = 4ma 0.4 v rst leakage current rst = 5v 0.025 1 a rst rise time r pullup = 10k to 3.3v 0.05 s rst fall time r pullup = 10k to 3.3v 0.05 s pgood/rst timing rising vin/vout rising threshold to pgood high rising 100 200 300 ms pgood rising to rst rising 1.0 s pgood/rst timing falling v in /v out falling threshold to p good falling 35 70 110 s pgood falling to rst falling 4.5 5.5 6.5 s overvoltage protection ov trip point 118 % overcurrent protection overcurrent threshold (ocset_) (note 8) r ocset = 55k ? 32 a full-scale input current (isen_) (note 8) 15 a overcurrent set voltage (ocset_) 1.70 1.75 1.80 v over-temperature over-temperature shutdown 150 c over-temperature hysteresis 20 c notes: 6. in normal operation, where the device is supplied with voltag e on the v in pin, the vcc_5v pin provides a 5v output capable of 60ma (min) . when the vcc_5v pin is used as a 5v supply input, the internal ldo regulator is disabled and the v in input pin must be connected to the vcc_5v pin. (refer to thepin descriptions on page 9 for more d etails.) 7. this is the total shutdown current with v in = 5.6 and 24v. 8. operating current is the s upply current consumed when the dev ice is active but not switchi ng. it does not include gate drive current. 9. limits established by characte rization and are not production tested. 10. check note 6 for vcc_5v and vin configurations at 5v 10% in put applications. ISL9440B, isl9440cs pgood signal will fall l ow when vin pin voltage drops below 5.55v ( typ), which results from the ear ly warning detection on vin pin voltage. 11. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested. electrical specifications recommended operating conditions unless otherwise noted. refer to block diagram on page 3, typical application - ISL9440B on page 4 and typical application - isl 9440c on page 5. v in = 5.6v to 24v, or vcc_5v = 5v 10%, c_vcc_5v = 4.7f, t a = -40c to +85c, typical values are at t a = +25c. (continued) parameter test conditions min (note 11) typ max (note 11) units
ISL9440B, isl9440c fn6799 rev 4.00 page 9 of 25 february 18, 2016 pin descriptions boot3, boot2, boot1 (pin 20, 26, 31) these pins are bootstrap pins to provide bias for high side driver. the bootstrap diodes are integrated to help reduce tota l cost and reduce layout complexity. ugate3, ugate2, ugate1 (pins 21, 27, 30) these pins provide t he gate drive for the upper mosfets. phase3, phase2, phase1 (pins 19, 25, 32) these pins are connected to the junction of the upper mosfets source, output filter inductor, and lower mosfets drain. lgate3, lgate2, lgate1 (pins 22, 28, 29) these pins provide the gate drive for the lower mosfets. pgnd (pin 23) this pin provides the power ground connection for the lower gate drivers for all pwm1, pwm 2 and pwm3. this pin should be connected to the sources of t he lower mosfets and the (-) terminals of the exter nal input capacitors. fb3, fb2, fb1, ldofb (pin 16, 13, 6, 10) these pins are connected to the feedback resistor divider and provide the voltage feedback signals for the respective controller. they set the output voltage of the converter. in addition, the pgood circuit uses these inputs to monitor the output voltage status. isen3, isen2, isen1 (pin 18, 24, 1) these pins are used to monit or the voltage drop across the lower mosfet for current loop feedback and overcurrent protection. pgood (pin 2) this is an open drain logic output used to indicate the status of the output voltages a nd input voltage. this pin is pulled low when any of the three pwm outpu ts is not within 10% of the respective nominal vol tage, or if the linear controller output is less than 75% of its nominal val ue, or vin pin voltage drops below 5.55v. the pgood pin also indicates t he vin pin status for early warning function. if the voltage on vin pin drops below 5.55v, this pin will be pulled low. sgnd (pin 11) this is the small-signal ground, common to all 4 controllers, and is suggested to be routed separately from the high current ground (pgnd). in case of one whole solid ground and no noisy current going through around chip, sgnd and pgnd can be tied to the same ground copper plane. all voltage levels are measured with respect to this pin. a small ceramic capacitor should be connected ri ght next to this pin for noise decoupling. vin (pin 4) use this pin to power the devi ce with an external supply voltage with a range of 5.6v to 24v. for 5v 10% operation, connect this pin to vcc_5v. for ISL9440B and isl9440c, th e voltage on t his pin is monitored for early warning func tion. if the voltage on this pi n drop below 5.55v, the pgoo d will be pulled low. rst will be low after pgood toggles to lo w for 5.5s (typ). refer to figure 1 for detailed time sequence. vcc_5v (pin 3) this pin is the output of the in ternal 5v linear regulator. thi s output supplies the bias for the ic, the low-side gate drivers, and the external boot circuitry for the high-side gate drivers. the ic may be powe red directly from a single 5v (10%) supply at this pin. when used a s a 5v supply i nput, this pin must be externally connected to v in . the vcc_5v pin must be always decoupled to power ground with a minimum of 4.7f ceramic capacitor, place d very close to the pin. en/ss3, en/ss2, en/ss1 (pin 17, 14, 5) these pins provide an enable/disable function and soft starting for their respective pwm outputs. the output is disabled when the pin is pulled to gnd. when a capacitor is connected from one of these pins to the ground, a regulat ed 1.55a soft-start current charges this capacitor d uring soft starting. when the voltage on the en/ssx pin reaches 1.3v, the corresponding pwm output is active. from 1.3v to 2.1v, the reference voltage of the corresponding pwm chan nel is clamped to the voltage at en/ssx minus 1.3v. the cap acitance of the soft-start capacitors sets the soft-startin g time and enable delay time. setting the soft-starting time too short might create undesirab le overshoot at the output during start-up. it is recommended that the soft-starting time be greater than 1.0ms. please do not flo at this pin. the typical soft-start time is set according to equation 1: g4 (pin 9) this pin is the open drain ou tput of the linear regulator controller. ocset3, ocset2, ocset1 (pin 15, 12, 7) a resistor from this pin to ground sets the overcurrent thresho ld for the respective pwm. rst (pin 8) reset pulse output. this pin out puts a logic low signal after pgood toggles to low for 5.5s (typ). it can be used to reset system. refer to figure 1 for detailed time sequence with early warning function. t ssx 0.8v c ssx 1.55 ? a ------------------- - ?? ?? = (eq. 1)
ISL9440B, isl9440c fn6799 rev 4.00 page 10 of 25 february 18, 2016 figure 1. pgood and rst timing 0 5 10 15 20 25 8 7 6 5 4 3 2 1 0 voltage (v) time (not to scale) v in = 5.5v falling/ v out 1-4 out of regulation v in = 5.5v rising/ v out 1-4 in regulation v in = 5.5v rising/ v out 1-4 in regulation typ = 200ms 2.4v 0.4v max = 2s max = 100s max = 6.5s v in /v out rst pgood typical performance curves (oscilloscope plots are taken using the ISL9440Beval1z evaluati on board, v in = 19v unless otherwise noted). figure 2. pwm1 load regulation figure 3. pwm1 efficiency vs load (v o = 5.0v), rjk0305dpb for upper mosfet and rjk0301dpb for lower mosfet figure 4. pwm2 load regulation figure 5. pwm2 efficiency vs load (v o = 3.3v), rjk0305dpb for upper mosfet and rjk0301dpb for lower mosfet load current (a) 4.95 4.96 4.97 4.98 4.99 5.00 5.01 5.02 5.03 5.04 5.05 0 8 12 16 output voltage (v) v in = 19v v in = 12v v in = 6v 4 60 65 70 75 80 85 90 95 100 0 4 6 8 10 12 14 16 load current (a) efficiency (%) v in = 23vdc v in = 16vdc 2 v in = 19vdc 3.30 3.31 3.32 3.33 3.34 3.35 3.36 0 8 12 16 output voltage (v) load current (a) 4 v in = 12v v in = 5v v in = 19v 60 65 70 75 80 85 90 95 100 0 8 10 12 14 16 load current (a) efficiency (%) 246 v in = 16vdc v in = 19vdc v in = 23vdc
ISL9440B, isl9440c fn6799 rev 4.00 page 11 of 25 february 18, 2016 figure 6. pwm3 load regulation figure 7. pwm3 efficiency vs load (v o = 12v), rjk0304dpb for upper mosfet and rjk0301dpb for lower mosfet figure 8. vcc_5v vs supply figure 9. operating current vs v in (rpg = rrst = 100k ??? r ocset = 121k ? ) figure 10. soft-start current vs ven/ss figure 11. normalized out put voltage vs ven/ss typical performance curves (continued) (oscilloscope plots are taken using the ISL9440Beval1z evaluati on board, v in = 19v unless otherwise noted). load current (a) output voltage (v) 11.90 11.92 11.94 11.96 11.98 12.00 12.02 12.04 12.06 12.08 12.10 0 8 12 16 4 v in = 15v v in = 19v v in = 23v 60 65 70 75 80 85 90 95 100 0 4 8 10 12 14 load current (a) efficiency (%) v in = 16vdc v in = 19vdc v in = 23vdc 26 4.00 4.25 4.50 4.75 5.00 5.25 0 1020304050 load current (a) vcc_5v supply (v) v in = 4.5v v in = 5.0v v in = 5.5v v in = 24v 3.0 3.5 4.0 4.5 5.0 4 7 10 13 16 19 22 25 operating current (ma) input voltage (v) soft-start current (a) ven/ss (v) 0.5 0.8 1.1 1.4 1.7 2.0 0234 v in = 12v 1 0 10 20 30 40 50 60 70 80 90 100 110 1.00 1.25 1.50 1.75 2.00 2.25 normalized output (%) v in = 24v v in = 15v v in = 12v 2.50 ven/ss (v)
ISL9440B, isl9440c fn6799 rev 4.00 page 12 of 25 february 18, 2016 figure 12. shutdown current vs v in (pgood and rst floating) figure 13. pwm soft-start waveforms, c ss = 22nf figure 14. phase node pwm waveforms, v in = 24v figure 15. pwm soft-start waveforms, pre-biased, c ss = 22nf figure 16. pgood rising after start up figure 17. pgood falling to rst falling typical performance curves (continued) (oscilloscope plots are taken using the ISL9440Beval1z evaluati on board, v in = 19v unless otherwise noted). shutdowns current (a) v in (v) 0 20 40 60 80 100 120 0 5 10 15 20 25 v out3 , 5.0v/div 5.0ms/div v out2 , 2.0v/div v out4 (ldo), 2.0v/div v out1 , 2.0v/div 1.0s/div pwm1, 10v/div pwm2, 10v/div pwm3, 10v/div v out3 , 2.0v/div 5ms/div v out1 , 2.0v/div v out2 , 2.0v/div v cc5v , 5.0v/div 50ms/div v out1 , 2.0v/div v out2 , 2.0v/div v out2 , 2.0v/div pgood, 5.0v/div 10 s /div pgood, 5.0v/div rst , 5.0v/div v out1 , 2.0v/div
ISL9440B, isl9440c fn6799 rev 4.00 page 13 of 25 february 18, 2016 figure 18. pgood rising to rst rising figure 19. v in falling to pgood falling delay time figure 20. pwm1 output ripple under max load (v in = 23v, i o1 = i o2 = 15a, i o3 = 12a, full bandwidth ) figure 21. pwm1 load transient response (load step from 3.75a to 11.25a) figure 22. pwm2 output ripple under max load (v in = 23v, i o1 = i o2 = 15a, i o3 = 12a, full bandwidth) figure 23. pwm2 load transient response (load step from 3.75a to 11.25a) typical performance curves (continued) (oscilloscope plots are taken using the ISL9440Beval1z evaluati on board, v in = 19v unless otherwise noted). 2.0s/div pgood, 5.0v/div rst , 5.0v/div v out1 , 2.0v/div pgood, 5.0v/div v in , 2.0v/div rst , 5.0v/div v out1 , 2.0v/div 0.5ms/div v out1 (ac), 50mv/div 2.0 s /div v out1 (ac), 100mv/div i step , 5.0a/div 50 s /div v out2 (ac), 50mv/div 2.0 s /div i step , 5.0a/div 50 s /div v out2 (ac), 100mv/div
ISL9440B, isl9440c fn6799 rev 4.00 page 14 of 25 february 18, 2016 figure 24. pwm3 output ripple under max load (v in = 23v, i o1 = i o2 = 15a, i o3 = 12a, full bandwidth) figure 25. pwm3 load transient response (load step from 3a to 9a) figure 26. pwm1 overcurrent protection entry waveform figure 27. pwm1 overcurrent protection recovery waveform figure 28. ldo load regulation figure 29. ldo load transient (load step from 0.1a to 0.6a) typical performance curves (continued) (oscilloscope plots are taken using the ISL9440Beval1z evaluati on board, v in = 19v unless otherwise noted). v out3 (ac), 50mv/div 2.0 s /div v out3 (ac), 200mv/div i step , 5.0a/div 50 s /div v out , 5.0v/div pgood, 5.0v/div i out , 20a/div en/ss1, 5.0v/div v out , 5.0v/div i out , 20a/div en/ss1, 5.0v/div pgood, 5.0v/div output voltage (v) 2.45 2.46 2.47 2.48 2.49 2.50 2.51 2.52 2.53 2.54 2.55 0 0.2 0.4 0.6 0.8 1.0 load current (a) v in = 4.5v v in = 24v v in = 12v v out (ac), 20mv/div i step , 0.5a/div 100 s /div
ISL9440B, isl9440c fn6799 rev 4.00 page 15 of 25 february 18, 2016 figure 30. switching frequency vs v in figure 31. soft-start current vs temperature figure 32. switching frequency vs temperature figure 33. vcc_5v vs temperature figure 34. shutdown current vs temperature figure 35. reference voltage vs temperature typical performance curves (continued) (oscilloscope plots are taken using the ISL9440Beval1z evaluati on board, v in = 19v unless otherwise noted). v in (v) switching frequency (khz) 270 285 300 330 5 10152025 315 temperature (c) soft-start current (a) 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 -50 -25 0 25 50 75 100 v ss = 0v, v in = 12v v ss = 2v, v in = 12v v ss = 1.3v, v in = 12v temperature (c) switching frequency (khz) 200 220 240 260 280 300 320 340 360 -50 0 50 100 v in = 19v/0a load v in = 12v/0a load vcc_5v supply (v) temperature (c) 4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25 -50 0 50 100 v in = 19.0v/0a load v in = 12.0v/0a load temperature (c) shutdown current (a) 60 62 64 66 68 70 72 74 76 78 80 -50 0 50 100 v in = 12v temperature (c) reference voltage (mv) 792 796 800 804 808 -50 0 50 100
ISL9440B, isl9440c fn6799 rev 4.00 page 16 of 25 february 18, 2016 typical performance curves of isl9440c (oscilloscope plots are taken using the isl9440ceval1z evaluati on board, v in = 12v unless otherwise noted). figure 36. pwm1 efficiency vs load (v o = 1.0v, irf7907 for upper mosfet and lower mosfet) figure 37. pwm2 efficiency vs load (v o = 3.3v, irf7907 for upper mosfet and lower mosfet) figure 38. pwm3 efficiency vs load (v o = 5.0v, irf7907 for upper mosfet and lower mosfet) figure 39. switching frequency vs v in figure 40. switching frequency vs temperature efficiency (%) load current (a) 40 45 50 55 60 65 70 75 80 85 90 08 v in = 9vdc v in = 16vdc v in = 12vdc 1234567 efficiency (%) 50 55 60 65 70 75 80 85 90 95 100 load current (a) 08 1234567 v in = 16vdc v in = 12vdc v in = 9vdc load current (a) efficiency (%) 50 55 60 65 70 75 80 85 90 95 100 0246 5 3 1 v in = 16vdc v in = 12vdc v in = 9vdc v in (v) switching frequency (khz) 540 570 600 630 660 5 10152025 temperature (c) switching frequency (khz) 400 440 480 520 560 600 640 680 720 -50 0 50 100 v in = 19.0v/0a load v in = 12.0v/0a load
ISL9440B, isl9440c fn6799 rev 4.00 page 17 of 25 february 18, 2016 functional description general description the ISL9440B and isl9440c integrate control circuits for three synchronous buck converters and one linear controller. the three synchronous bucks operate ou t-of-phase to substantially reduce the input ripple and t hus reduce the input filter requirements. each part has 3 control lines (en/ss1, en/ss2 and en/ss3), which provide independent control and programmable soft-start for each of the synchronous buck outputs. the buck pwm controllers employ free-running frequency of 300khz (ISL9440B) and 600khz (isl9440c). the current mode control scheme with an inpu t voltage feed-forward ramp input to the pwm modulator provides an excellent rejection of input voltage variations and simplifies loop compensation design. the linear controller can drive either a pnp bipolar junction transistor or p-channel mosfet to provide ul tra low-dropout regulation with programmable voltages. internal 5v linear regulator (vcc_5v) all ISL9440B and isl9440c fun ctions are internally powered from an on-chip, low dropout 5v regulator. the maximum regulator input voltage is 24v. bypass the regulators output (vcc_5v) with a 4.7f capacitor to gro und. the dropout voltage for this ldo is typically 600mv, so when v in is greater than 5.6v, vcc_5v is typically 5v. the ISL9440B and isl9440c also employ an underv oltage lockout circuit that disables both regulators w hen vcc_5v falls below 3.7v. the internal ldo can source o ver 60ma to s upply the ic, power the low-side gate drivers and charge the external boot capacitor. when driving large fets especially at 300khz frequency, little or no regulator cur rent may be available for external loads. for example, a singl e large fet with 15nc t otal gate charge requires 15nc x 300khz = 4. 5ma (15nc x 600khz = 9ma). also, at higher input voltages with larger fets, the power dissipation across the internal 5v will increase. excessive dissipation across this regulator must be avoided to prevent junction temperature rise. lar ger fets can be used with 5v 10% input applicatio ns. the thermal ov erload protection circuit will be triggered, if the vcc_5v output is short-circui t. connect vcc_5v to v in for 5v 10% input applications. enable signals and soft-start operation the typical applications for t he ISL9440B and isl9440c are using programmable analog soft-s tart. the soft-start time can be set by the value of t he soft-start capacitors connected from the en/ssx pins to the ground. the start-up in-rush current can be alleviated by adjusting the soft starting time. after the vcc_5v pin reaches the uvlo thre shold, the ISL9440B and isl9440c soft-star t circuitry becomes active. the internal 1.55a charge cu rrent begins charging up the soft-start capacitors connect ed from the en/ssx pin to the gnd. the pwm output remains ina ctive until the voltage on the corresponding en/ssx pin r eaches 1.3v. after that, the reference voltage is clamped to t he voltage on the en/ssx pin minus 1.3v. then the output voltage ramps up with the voltage on en/ssx until the voltage reaches 2.1v. the charging continues until the voltage on the en/ ssx reaches 3.5v. each pwm output can be d isabled by pulling the corresponding en/ssx to the ground. pgood will not toggle to high unt il soft-start is complete and all the four outputs are up and in regulations. output voltage programming the ISL9440B and isl9440c us e a precision internal reference voltage to set the output voltage. based on this internal reference, the output v oltage can thus be set from 0.8 v up to a level determined by t he input voltage, the maximum duty cycle, and the conversion efficiency of the circuit. a resistive divider from the o utput to ground se ts the output voltage of either pwm channel. th e center point of the divider shall be connected to the fbx pin. the outpu t voltage value is determined by equation 2. where r1 is the top resistor o f the feedback divider network and r2 is the resistor connected from fbx to ground. out-of-phase operation to reduce input ripple curren t, channel 1 and ch annel 2 operate 180 out-of-phase, channel 3 k eeps 0 phase with channel 1. channel 1 and channel 2 typica lly output higher load compared to channel 3 because o f their stronger drivers. this reduces th e input capacitor rippl e current requireme nts, reduces power supply-induced noise, and improves emi. this effectively helps to lower component cost, save b oard space and reduce emi. triple pwms typically operate in -phase and turn on both upper fets at the same time. the input capacitor must then support th e instantaneous current requirem ents of the three switching regulators simultaneously, result ing in increased ripple voltag e and current. the higher rms rippl e current lowers the efficienc y due to the power loss associat ed with the esr of the input capacitor. this typica lly requires more low-esr capacitors in parallel to minimize the input voltage ripple and esr-related losses, or to meet the requi red ripple current rating. with synchronized out-of-phase operation, the high-side mosfets turn on 180 out-of- phase. the instantaneous input current peaks of both regulators n o longer overlap, resulting i n reduced rms ripple current and input voltage ripple. this reduc es the required input capacitor rip ple current rating, allowing fe wer or less expensive capacitors, and reducing the shielding requirements for emi. the typic al operating curves show the synchronized 180 out -of-phase operation. v outx 0.8v r1 r2 + r2 ---------------------- ?? ?? = (eq. 2)
ISL9440B, isl9440c fn6799 rev 4.00 page 18 of 25 february 18, 2016 input voltage range the ISL9440B and isl9440c ar e designed to operate from input supplies rangin g from 4.5v to 24v. for 5v 10% input applications, the isl9441 is suggested. the reason is that v in and vcc_5v pin shoul d be tied together for this input applicatio n. the early warning function will pull pgood and rst low for ISL9440B and isl9440c. the input voltage range can be effectively limited by the available maximum duty cycle (d max = 93% for ISL9440B, and d max = 86% for isl9440c), as shown in equation 3. where: v d1 = sum of the parasitic voltage drops in the inductor discharge path, including the lower fet, inductor and pc board. v d2 = sum of the voltage drops in the charging path, including the upper fet, inductor a nd pc board resistances. the maximum input voltage an d minimum output voltage is limited by the mi nimum on-time (t on(min) ).(see equation 4). where, t on(min) = 30ns gate control logic the gate control logic translat es generated pwm signals into ga te drive signals providing amplific ation, level shifting and shoot - through protection. the gate driv ers have some circuitry that helps optimize the ic performa nce over a wide range of operational conditions. as mosf et switching times can vary dramatically from ty pe to type and with i nput voltage, the gate control logic provides adaptive dead-time by monitoring real ga te waveforms of both the upper and the lower mosfets. shoot- through control logic provides a 20ns dead-time to ensure that both the upper and lower mosfets will not turn on simultaneously and cause a shoot-through condition. gate drivers the low-side gate driver is suppl ied from vcc_5v and provides a peak sink current of 2a/2a/2 00ma and source current of 800ma/800ma/400ma for channels 1, 2, 3 respectively. the high-side gate driver i s also capable of delivering the same current as those in low-side gat e driver. gate-drive voltages f or the upper n-channel mosfet are generated by the flying capacitor boot circuit. a boot c apacitor connected from the boot pin to the phase node provides power to the high-side mosfet driver. to limit the peak current in the ic, an external resistor may be placed between t he ugate pin and the gate of the external mosfet. this small series resistor also damps any oscillations caused by the resonant tank of the parasitic inductances in the traces of the board and the fets input capacitance. at start-up, the low -side mosfet turns o n and forces phase to ground in order to charge t he boot capacitor to 5v. after the low-side mosfet turns of f, the high-side mosfet is turned on by closing an inter nal switch between boot and ugate. this provides the necessary gate-to-source voltage to turn on the upper mosfet, an action that boos ts the 5v gate drive signal above vin. the current required to drive the upper mosfet is drawn from the internal 5v regulator. adaptive dead time the ISL9440B and isl9440c incorporate an adaptive dead-time algorithm on the synchronous buck pwm controllers that optimizes operation with va rying mosfet conditions. this algorithm provides an approx imately 20ns of dead-time between switching the upper and lower mosfets. this dead time is adaptive and allows oper ation with different mosfets without having to externally a djust the dead-time using a resistor or capacitor. during tu rn-off of the lo wer mosfet, the lgate voltage is moni tored until it reaches a 1v threshold, at which time the ugate is releas ed to rise. adaptive dead time circuitry monitors the upper m osfet gate voltage during ugate turn-off. once the u pper mosfet gate-to-source voltage has dropped below a threshold of 1v, the lgate is allowed to rise. internal bootstrap diode the ISL9440B and isl9440c have integrated bootstrap diodes to help reduce total cost and re duce layout compl exity. simply adding an external capacitor across the boot and phase pins completes the bootstrap circ uit. the bootstrap capacitor must have a maximum volta ge rating above the maximum battery voltage plus 5v. the bootstrap capacitor can be chosen from equation 5. v in min ?? v out v d1 + 0.93 -------------------------------- ?? ?? v d2 v d1 C + = (eq. 3) v in max ?? v out t on min ?? 300khz ? --------------------------------------------------- - ? (eq. 4) boot ugate phase vcc_5v vin ISL9440B figure 41. c boot q gate ? v boot ----------------------- - ? (eq. 5)
ISL9440B, isl9440c fn6799 rev 4.00 page 19 of 25 february 18, 2016 where q gate is the amount of gate c harge required to fully charge the gate of t he upper mosfet. the ? v boot term is defined as the allowable droop in the rail of the upper drive. as an example, suppose an upper mosfet has a gate charge (qgate) of 25nc at 5v and also assume the droop in the drive voltage over a pwm cycle is 200mv. one will find that a bootstrap capacitance of at leas t 0.125f is required. the next larger standard value capacit ance is 0.22f. a good quality ceramic capacitor is recommended. protection circuits the converter output is monitored and protected against overload, short circuit and undervoltage conditions. a sustained overload on the output sets the pgood low and initiates hiccup mode. undervoltage lockout the ISL9440B and isl9440c in clude vcc uvlo protection that will keep the devices in a reset condition until a proper operating voltage is applied and that will also shut down the ISL9440B and isl9440c if the operating voltage drops below a pre-defined value. all controlle rs are disabled when uvlo is asserted. when uvlo is asse rted, pgood will be valid and de-asserted. overcurrent protection all the pwm controllers use the lower mosfets on-resistance, r ds(on) , to monitor the current in the converter. the sensed voltage drop is compared with a threshold set by a resistor connected from the ocsetx pin to ground. where, i oc is the desired overcurrent protection threshold, and r cs is a value of the current sen se resistor connected to the isenx pin. when an overcurrent is detected, the upper mosfet remains off and the lower mosfet remai ns on until the current drops below i oc . as a result, the converter skips pwm pulses. when the overload conditi on is removed, the converter will resume normal operation. this action will protect the converter agains t overcurrent conditions at tempo rary overload or during high di/dt load transient. the conv erter remains active and can return to normal operation immediately after the overcurrent is removed. when the overload condition persi sts or at output short circuit conditions, the overcurrent co ndition lasts for more than 2 consecutive cycles. when the ov ercurrent is detected for 2 consecutive clock cycles, the ic enters a hiccup mode by turning off the gate drivers and entering into soft-start. the ic will cycle 5 times through soft-s tart before trying to restart. the ic will continue to cycle throug h soft-start unt il the overcurr ent condition is removed. hiccup mode is active during soft-start so care must be taken to ensure that the peak inductor current does not exceed the overcurrent threshold during soft-start. because of the nature of this current sensing technique, and to accommodate a wide range of r ds(on) variations, the value of the overcurrent threshold should represent an overload current about 150% to 180% of the maxi mum operating current. if more accurate curren t protection is desir ed, place a current sense resistor in series with the lower mosfet source and connect r cs to the source of the mosfet. overvoltage protection all switching controllers wit hin the isl9440 b and isl9440c have fixed overvoltage set point s. the overvoltage set point is set at 118% of the nominal outpu t voltage, the output voltage set by the feedback resistors. in the case of an overvoltage event, the ic will attempt to br ing the output voltage back int o regulation by keeping the upper mosfet turned off and modulating the lower mosfet f or 2 consecutive pwm cycles. if the overvoltage co ndition has not been corrected in 2 cycles and the output voltage is abo ve 118% of the nominal output voltage, the ISL9440B and isl944 0c will turn off both the upper mosfet and the lower mosfet. the ISL9440B and isl9440c will enter hiccup mode until the output voltage return to 110% of the nominal output voltage. over-temperature protection the ic incorporates an over-t emperature prot ection circuit that shuts the ic down when a die temperature of +150c is reached. normal operation resumes when the die temperatures drops below +130 c through the initiation of a full soft-start cycle. feedback loop compensation to reduce the number of externa l components and to simplify the process of determining compensation components, all pwm controllers have internally com pensated error amplifiers. to make internal compensation possi ble several design measures were taken. first, the ramp signal applie d to the pwm comparator is proportional to the input voltage provided via the vin pin. thi s keeps the modulator gain consta nt with variation in the input voltage. second, the load current proportional signal is derive d from the voltage dr op across the lower mosfet during the pwm time interval and is subtra cted from the amplified error signal on the comparator input. this creates an internal curren t control loop. the resistor conn ected to the isen pin sets the gain in the current feedback lo op. equation 7 estimates the required value of the current s ense resistor depending on the maximum operating load cu rrent and the value of the mosfets r ds(on) . choosing r cs to provide 30a of current to the current sample and hold circuitry is recomme nded, but values down to 2a r ocset 7 ?? r cs ?? i oc ?? r ds on ?? ?? ------------------------------------------ - = (eq. 6) r cs i max ?? r ds on ?? ?? 30 ? a ---------------------------------------------- - ? (eq. 7)
ISL9440B, isl9440c fn6799 rev 4.00 page 20 of 25 february 18, 2016 and up to 100a can be used. the higher sampling current will help to stabilize the loop. due to the current loop feedback, the modulator has a single pole response with -20db slope at a frequency determined by the load, as shown in equation 8. where, r o is load resistance and c o is load capacitance. for this type of modulator, a type 2 compensation circuit is usuall y sufficient. figure 42 shows a type 2 amplifier and its response along with the responses of the curr ent mode modulator and the converter. the type 2 amplifier, in addition to the pole at ori gin, has a zero-pole pair that cau ses a flat gai n region at frequencies in between th e zero and the pole. the zero frequency, the amplifier high-frequency gain, and the modulator gain are chosen to sati sfy most typical applications. the crossover frequency will a ppear at the point where the modulator attenuation equals t he amplifier high frequency gain. the only task that the syst em designer has to complete is to specify the output filter capacitors to position the load ma in pole somewhere within one dec ade lower than the amplifier zero frequency. with this type of compensation plenty of phase margin is easily achieved due to zero-pole pair phase boost. conditional stability may occur only when the main load pole is positioned too much to the left s ide on the fr equency axis due to excessive output fil ter capacitance. in this case, the esr zero placed within the 1.2k hz to 30khz range gives some additional phase boost. some phase boost can also be achieved by connecting capacitor c z in parallel with the upper resistor r 1 of the divider that sets t he output voltage value. please refer to output capacitor selection on page 22 and input capacitor selection on page 23 for further details. linear regulator the linear regulator controller is a trans-conductance amplifie r with a nominal gain of 2a/v. the n-channel mosfet output buffer can sink a minimum of 50ma. the reference voltage is 0.8v. w ith 0v different ial at its inpu t, the controller sinks 21ma of current. for better load regulatio n, it is recommended that the resi stor from the ld o input to the base of the pnp (or gate of the pfet) is set so that the sink current at g4 pin is within 9ma to 31ma over the entire load and temperature range. an external pnp transistor or p-channel mosfet pass device can be used. the dominant pole for the loop can be placed at the base of the pnp (or gate of the pfet), as a capacitor from emitter-to-base (source to gate of a pfet). better load transient response is achieved however, if the dominant pole is placed at the output with a capacitor to ground at the output of the regulator. under no-load conditions, leak age currents from the pass transistors supply the outpu t capacitors, even when the transistor is off. generally, t his is not a problem since the feedback resistor drains the excess charge. however, charge may build up on the outpu t capacitor making v ldo rise above its set point. care must be tak en to insure that the feedback resistors current exceeds the pass transistors leakage current over the entire temperature range. f po 1 2 ? r o c o ?? -------------------------------- - = (eq. 8) f z 1 2 ? r 2 c 1 ?? ------------------------------ - 6khz == (eq. 9) f p 1 2 ? r 1 c 2 ?? ------------------------------ - 600khz == (eq. 10) figure 42. feedback loop compensation r1 r2 c1 c2 f po f z f p f c modulator ea converter type 2 ea g ea = 18db g m = 17.5db 0.79 0.8 0.82 0.83 0.85 0 40 60 feedback voltage (v) error amplifier sink 20 50 30 10 current (ma) 0.81 0.84 figure 43. linear controller gain
ISL9440B, isl9440c fn6799 rev 4.00 page 21 of 25 february 18, 2016 the linear regulator output can be supplied by the output of one of the pwms. when using a pfet, the output of the linear regulator will track the pwm supply after the pwm output rises to a voltage greater than the threshold of the pfet pass device. the voltage different ial between the pwm and the linear output will be the load current times the r ds(on) . base-drive noise reduction the high-impedance base driver is susceptible to system noise, especially when the lin ear regulator is lightly loaded. capacitively coupled switching noise or inductively coupled emi onto the base drive causes fluctuations in the base current, which appear as noise on the linear regulators output . keep the base drive traces away from the step-down converter, and as short as possible, to minimize noise coupling. a resistor in series with the gate drivers reduces th e switching noise generated by pwm. additionally, a bypass capacitor may be placed across th e base-to-emitter resistor. this bypass capacitor, in addi tion to the transistors input capacitor, could bring in a second pole that will destabilize t he linear regulator. therefore, t he stability requirements determi ne the maximum base-to-emitter capacitance. layout guidelines careful attention to layout requirements is necessary for successful implementation of an ISL9440B and isl9440c based dc/dc converter. the ISL9440B and isl9440c switch at a very high frequency and therefore, the switching times are very short. at these switching frequencies, even the shortest trace has significant impedance . also, the peak gate drive current rises significantly in an extremely short time. transit ion speed of the current from on e device to another causes voltage spikes across the inte rconnecting impedances and parasitic circuit elements. these voltage spikes can degrade efficiency, generate emi, increa se device overvoltage stress and ringing. careful component selection and proper pc board layout minimizes the magnit ude of these voltage spikes. there are three se ts of critical com ponents in a dc/dc converter using the ISL9440B and isl9440c: the controller, the switching power compon ents and the small signal components. the switching powe r components are the most critical from a layout point of view because they switch a larg e amount of energy so they tend to generate a large amount of noise. the critical small si gnal components are those connected to sensitive nodes or those supplying critical bias currents. a multi-layer printed circuit board is recommended. layout considerations 1. the input capacitors, upper fet, lower fet, inductor and output capacitor should be placed first. isolate these power components on the topside of the board with their ground terminals adjacent to one another. place the input high frequency decoupling ceramic capacitor very close to the mosfets. 2. use separate ground planes for power ground and small signal ground. connect t he sgnd and pgnd together close to the ic. do not conne ct them together anywhere else. 3. the loop formed by input capa citor, the top fet and the bottom fet must be kept as small as possible. 4. ensure the current paths fro m the input capacitor to the mosfet, to the output inductor and output capacitor are as short as possible with maximu m allowable trace widths. 5. place the pwm controller i c close to lower fet. the lgate connection should be short and wide. the ic can be best placed over a quiet gro und area. avoi d switching ground loop current in this area. 6. place vcc_5v bypass capacitor very close to vcc_5v pin of the ic and connect its gro und to the pgnd plane. 7. place the gate drive components boot diode and boot capacitors together near controller ic. 8. the output capacitors should be placed as close to the load as possible. use short wide copper regions to connect output capacitors-to-load to avoid inductance and resistances. 9. use copper filled polygons or wide but short trace to connect the juncti on of upper fet, low er fet and output inductor. also keep the phase node connection to the ic short. do not unnecessarily oversize the copper islands for phase node. since the phase no des are subjected to very high dv/dt voltages, the st ray capacitor formed between these islands and t he surrounding circuitry will tend to couple switching noise. 10. route all high speed switching nodes away from the control circuitry. 11. create a separate small anal og ground plane near the ic. connect the sgnd pin to this plane. all small signal grounding paths including feedback resistors, current limit setting resistors and enx pul l-down resistors should be connected to t his sgnd plane. 12. separate current sensing traces from phase node connections 13. ensure the feedba ck connection to the output capacitor is short and direct. component selection guidelines mosfet considerations the logic level mosfets are chosen for optimum efficiency given the potentially wide input voltage range and output power requirements. two n-channel mos fets are used in each of the synchronous-rectified bu ck converters for the 3 pwm outputs. these mosfets sh ould be selected based upon r ds(on) , gate supply requirements, and thermal management considerations. the power dissipation inclu des two loss components; conduction loss and switchi ng loss. these losses are distributed between the upper and lower mosfets according to duty cycle (see equations 1 1 and 12). the conduction losses are the main component o f power dissipation for the lower mosfets. only the upp er mosfet has significant
ISL9440B, isl9440c fn6799 rev 4.00 page 22 of 25 february 18, 2016 switching losses, since the lower device tu rns on and off into near zero voltage. the equations assume linear voltage- current transitions and do not model power loss due to the reverse-recovery o f the lower mosfets body diode (see equations 11 and 12). a large gate-charge increa ses the switch ing time, t sw , which increases the upper mosfet switching losses. ensure that both mosfets are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package therma l-resistance specifications. output inductor selection the pwm converters require o utput inductors. the output inductor is selected to mee t the output voltage ripple requirements. the inductor val ue determines the converters ripple current and the ripple vol tage is a function of the ripp le current and output capacitor(s ) esr. the ripple voltage expression is given beginning in the output capacitor selection on page 22 and the ripple current is approximated by equation 13: output capacitor selection the output capacitors for each output have unique requirements. in general, the output capacit ors should be selected to meet t he dynamic regulation requirements including ripple voltage and load transients. selection of outp ut capacitors is also dependent on the output indu ctor, so some inductor analysis is required to s elect the output capacitors. one of the parameters limiting the converters response to a load transient is the time requ ired for the inductor current to slew to its new level. the ISL9440B and isl9440c will provide either 0% or maximum duty cycle in response to a load transient. the response time is the time i nterval required to slew the inductor current from an initial current value to the load curr ent level. during this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor(s). minimizing the response time can minimize the output capacitance required. also, if the load transient ri se time is slower than the inductor response time, as in a hard drive or cd drive, it reduces the requirement o n the output capacitor. the maximum capacitor value required to provide the full, rising step, transient load curr ent during the response time of the inductor is sh own in equation 14: where, c out is the output capacitor(s) required, l o is the output inductor, i tran is the transient load current step, v in is the input voltage, v o is output voltage, and dv out is the drop in output voltage allowed during the load transient. high frequency capacitors initiall y supply the tra nsient curren t and slow the load rate-of-change seen by the bulk capacitors. the bulk filter capacitor values are generally determined by th e esr (equivalent series resi stance) and voltage rating requirements as well as act ual capacitance requirements. the output voltage ripple is due to the inductor ripple current and the esr of the output c apacitors as defined by equation 15: where, ? i l is calculated in the outpu t inductor selection on page 22. high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. consult with the manufacturer of the load circuitry for specific decoupling requirements. use only specialized low-esr capacitors intended for switching- regulator applications at 3 00khz (ISL9440B)/600khz (isl9440c) for the bulk capaci tors. in most cases, multiple small-case electrolytic capacito rs perform better than a single large-case capacitor. the stability requirement on the selection of the output capacitor is that t he esr zero (f z ) be between 1.2khz and 30khz. this range is set by an internal, single compensation zero at 6khz. the esr z ero can be a factor of five on either side of the internal zero and still contri bute to increased pha se margin of the contro l loop. therefore: in conclusion, the output capacit ors must meet three criteria: 1. they must have sufficient bul k capacitance to sustain the output voltage during a load transient wh ile the output inductor current is slewing to the value of the load transient. 2. the esr must be sufficiently low to meet the desired output voltage ripple due to the output inductor current. 3. the esr zero should be placed, in a rather large range, to provide additional phase margin. the recommended output capacito r value for the ISL9440B and isl9440c is between 150f to 680f, to meet stability criteria p upper i o 2 ?? r ds on ?? ?? v out ?? v in --------------------------------------------------------------- i o ?? v in ?? t sw ?? f sw ?? 2 ----------------------------------------------------------- - + = (eq. 11) p lower i o 2 ?? r ds on ?? ?? v in v out C ?? v in --------------------------------------------------------------- --------------- - = (eq. 12) ? i l v in v out C ?? v out ?? f s ?? l ?? v in ?? --------------------------------------------------------- - = (eq. 13) c out l o ?? i tran ?? 2 2v in v o C ?? dv out ?? ---------------------------------------------------------- - = (eq. 14) v ripple ? i l esr ?? = (eq. 15) c out 1 2 ? esr ?? f z ?? ----------------------------------- - = (eq. 16)
ISL9440B, isl9440c fn6799 rev 4.00 page 23 of 25 february 18, 2016 with external compensation. u se of aluminum electrolytic (poscap) or tantalum type capa citors is reco mmended. use of low esr ceramic capacitors is possible but would take more rigorous loop analysis to ensure stability. input capacitor selection the important paramet ers for the bulk input capacitor(s) are the voltage rating and the rms current rating. for reliable operation, select bulk input capacitors with voltage and curren t ratings above the maximum input voltage and largest rms current required by the circuit . the capacitor voltage rating should be at least 1.25x great er than the maximum input voltage and 1.5x is a conserva tive guideline. the ac rms input current varies with the load. the total rms current supplied by the input capacit ance is shown in equations 17 and 18: where, dc is duty cycle of t he respective pwm. depending on the specifics of the input power and its impedance, most (or all) of this c urrent is supplied by the inp ut capacitor(s). figure 44 shows the advantage of having the pwm converters oper ating out-of-phase. if the converters were operating in-phase, the combined rms current would be the algebraic sum, which is a much larger value as shown. the combined out-of-phase current is the square root of the sum of the square of the individual reflected currents and is significantly less than the c ombined in-phase current. use a mix of input bypass capa citors to control the voltage ripple across the mosfets. use ceramic capacitors for the high frequency decoupling an d bulk capacitors to supply the rms current. small ceramic capa citors can be p laced very close to the upper mosfet to suppress the voltage induced in the parasitic circuit impedances. for board designs that allow through-hole components, the sanyo os-con ?? series offer low esr and good temperature performance. for surface mount designs, solid tantalum capacitors can be used, but c aution must be exercised with regard to the capacitor surge cu rrent rating. t hese capacitors must be capable of handling t he surge-current at power-up. the tps series available from avx is surge current tested. i rms i rms1 2 i rms2 2 + = (eq. 17) i rmsx dc dc 2 C i o ? = (eq. 18) figure 44. input rms current vs load 12345 3.3v and 5v load current input rms current 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 in phase out of phase 5v 3.3v
fn6799 rev 4.00 page 24 of 25 february 18, 2016 ISL9440B, isl9440c intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2009-2016. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. about intersil intersil corporation is a leading provider of innovative power management and precision analog solutions. the company's produc ts address some of the largest marke ts within the industrial and i nfrastructure, mobile computing and high-end consumer markets. for the most updated datasheet, application no tes, related documentation and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggesti ons for improving this datashe et by visiting www.intersil.com/ask . reliability reports are also a vailable from our website at www.intersil.com/support . revision history the revision history provided is for informational purposes onl y and is believed to be accurate, but not warranted. please go to the web to make sure that you have the latest revision. date revision change february 18, 2016 fn6799.4 updated the ordering information table on page 2. added revision history and about intersil sections. updated pod l32.5x5b to the latest revision. changes are as fol lows: -correct note 4 from dimensi on b applies... to dimension app lies... -added triangles around notes 4, 5 and 6
ISL9440B, isl9440c fn6799 rev 4.00 page 25 of 25 february 18, 2016 package outline drawing l32.5x5b 32 lead quad flat no-lead plastic package rev 3, 5/10 located within the zone indicate d. the pin #1 identifier may be unless otherwise specified, t olerance : decimal 0.05 tiebar shown (if present) i s a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metalliz ed terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing c onform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view 5.00 a 5.00 b index area pin 1 6 (4x) 0.15 32x 0.40 0.10 4 a 32x 0.23 m 0.10 c b 16 9 4x 0.50 28x 3.5 6 pin #1 index area 3 .30 0 . 15 0 . 90 0.1 base plane see detail "x" seating plane 0.10 c c 0.08 c 0 . 2 ref c 0 . 05 max. 0 . 00 min. 5 ( 3. 30 ) ( 4. 80 typ ) ( 28x 0 . 5 ) (32x 0 . 23 ) ( 32x 0 . 60) + 0.07 - 0.05 17 25 24 8 1 32

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